Cryptographic processor chip is a commonly used cryptographic processing device, mainly used for encryption of data using encryption algorithm. Cryptographic processor chips can mainly be divided into two categories in terms of architecture and design method. The first category is based on Application Specific Integrated Circuits (ASICs) and the second category is based on Instruction Set Architecture Processors (ISAPs). Among them, the ASIC method tends to be optimized for an algorithm, and thus the computing speed is far faster than the ISAP method. However, after the design in the ASIC method is completed, the hardware structure cannot be changed and cannot meet the flexibility requirements of the application scenario of password, thus once it is cracked, it can only be discarded. Meanwhile, the biggest advantage of a cryptographic processor implemented by ISAP is in terms of functional flexibility. This flexibility is often obtained at the expense of energy efficiency. That is, it is very difficult for such processors to overcome the major defect of low energy efficiency.
In order to balance the flexibility and energy efficiency, the reconfigurable processor has emerged based on ASIC and ISAP. The reconfigurable processor can strike a balance between ASIC and ISAP processors to achieve the best compromise for application.
Specifically, in the reconfigurable processor in the prior art, each reconfigurable cell (RC) is connected to a routing unit, and the routing unit controls input and output of the RC. The RCs may be configured to connect together with adjacent RCs to exchange data with each other. Also, the RCs may communicate directly with outside via First In First Out (FIFO) registers, or be directly connected to array cache for storage.
In order to improve the performance of the processor, the reconfigurable processor in the prior art often performs acceleration design through the pipeline technology, and can increase the data processing speed with less hardware resources. However, due to the adoption of the pipeline technology, the reconfigurable processor can only work under a synchronous timing, which prevents the reconfigurable processor from achieving its optimal performance and increases the possibility that the processor is physically attacked.